On the Inhibition of COVID-19 Protease by Indian Herbal Plants: An In Silico Investigation

COVID-19 has quickly spread across the globe, becoming a pandemic. This disease has a variable impact in different countries depending on their cultural norms, mitigation efforts and health infrastructure. In India, a majority of people rely upon traditional Indian medicine to treat human maladies due to less-cost, easier availability and without any side-effect. These medicines are made by herbal plants. This study aims to assess the Indian herbal plants in the pursuit of potential COVID-19 inhibitors using in silico approaches. We have considered 18 extracted compounds of 11 different species of these plants. Our calculated lipophilicity, aqueous solubility and binding affinity of the extracted compounds suggest that the inhibition potentials in the order; harsingar > aloe vera > giloy > turmeric > neem > ashwagandha > red onion > tulsi > cannabis > black pepper. On comparing the binding affinity with hydroxychloroquine, we note that the inhibition potentials of the extracts of harsingar, aloe vera and giloy are very promising. Therefore, we believe that these findings will open further possibilities and accelerate the works towards finding an antidote for this malady

FORCED STACK SLEEP TRANSISTOR (FORTRAN): A NEW LEAKAGE CURRENT REDUCTION APPROACH IN CMOS BASED CIRCUIT DESIGNING

Reduction in leakage current has become a significant concern in nanotechnology-based low-power, low-voltage, and high-performance VLSI applications. This research article discusses a new low-power circuit design the approach of FORTRAN (FORced stack sleep TRANsistor), which decreases the leakage power efficiency in the CMOS-based circuit outline in VLSI domain. FORTRAN approach reduces leakage current in both active as well as standby modes of operation. Furthermore, it is not time intensive when the circuit goes from active mode to standby mode and vice-versa. To validate the proposed design approach, experiments are conducted in the Tanner EDA tool of mentor graphics bundle on projected circuit designs for the full adder, a chain of 4-inverters, and 4-bit multiplier designs utilizing 180nm, 130nm, and 90nm TSMC technology node. The outcomes obtained show the result of a 95-98% vital reduction in leakage power as well as a 15-20% reduction in dynamic power with a minor increase in delay. The result outcomes are compared for accuracy with the notable design approaches that are accessible for both active and standby modes of operation